Field effect transistors are widely used in electronic circuitry. It is desirable to keep leakage currents in such devices as low as possible or eliminate them altogether, since such currents waste power. One leakage mechanism which results in a relatively small amount of leakage in metal oxide silicon (MOS) type field effect transistors (MOSFETs) is known as gate induced drain leakage (GIDL). In the prior art, because of the small amount of leakage involved, it typically was not necessary to provide additional circuitry for suppressing GIDL.
However, with the progression of the development of integrated circuit technology, GIDL has become of more concern. Thus, as devices with smaller and smaller feature sizes are developed, the ratio of leakage to operating current increases. At the same time, the trend into mobile applications requires a minimum power loss to support long battery life.
GIDL is caused by a relatively high gate to drain voltage difference generating electron-hole pairs in the overlap region of the gate and the drain. A similar effect may occur at the overlap region of the gate and source, but the gate to source voltage difference is usually small enough so that the gate induced source leakage (GISL) can be ignored. In GIDL, a leakage current is established between the drain and bulk (body) of the FET, while in GISL the leakage is between the source and bulk. The GIDL depends mainly on oxide thickness and gate to drain voltage difference. With lower voltage differences the GIDL becomes very small and can be ignored.
Although the present invention is not limited to any particular application, an area where it is useful is in the field of dynamic read only memories (DRAMs). Thus, high gate to drain voltages are found, for example, in the row path of DRAMs where voltage boosted above the normal supply voltage and negative voltages are used together in the same circuit.